DIVT=B_0x0, DIVS=B_0x0
RCC PLL1 dividers configuration register 2
| DIVS | PLL1 DIVS division factor Set and reset by software to control the frequency of the pll1_s_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVS+1) is even, With VCOH, for all DIVS values These bits can be written only when the PLL1DIVSEN = 0. 0 (B_0x0): pll1_s_ck = vco1_ck 1 (B_0x1): pll1_s_ck = vco1_ck / 2 (default after reset) 2 (B_0x2): pll1_s_ck = vco1_ck / 3 3 (B_0x3): pll1_s_ck = vco1_ck / 4 4 (B_0x4): pll1_s_ck = vco1_ck / 5 5 (B_0x5): pll1_s_ck = vco1_ck / 6 6 (B_0x6): pll1_s_ck = vco1_ck / 7 7 (B_0x7): pll1_s_ck = vco1_ck / 8 |
| DIVT | PLL1 DIVT division factor Set and reset by software to control the frequency of the pll1_t_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVT+1) is even, With VCOH, for all DIVT values These bits can be written only when the PLL1DIVTEN = 0. 0 (B_0x0): pll1_t_ck = vco1_ck 1 (B_0x1): pll1_t_ck = vco1_ck / 2 (default after reset) 2 (B_0x2): pll1_t_ck = vco1_ck / 3 3 (B_0x3): pll1_t_ck = vco1_ck / 4 4 (B_0x4): pll1_t_ck = vco1_ck / 5 5 (B_0x5): pll1_t_ck = vco1_ck / 6 6 (B_0x6): pll1_t_ck = vco1_ck / 7 7 (B_0x7): pll1_t_ck = vco1_ck / 8 |