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stm32 /stm32h7rs /STM32H7S /RCC /RCC_PLL1SSCGR

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Interpret as RCC_PLL1SSCGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MOD_PER0 (B_0x0)TPDFN_DIS1 0 (B_0x0)RPDFN_DIS1 0 (B_0x0)DWNSPREAD1 0INC_STEP

DWNSPREAD1=B_0x0, TPDFN_DIS1=B_0x0, RPDFN_DIS1=B_0x0

Description

RCC PLL1 Spread Spectrum Clock Generator register

Fields

MOD_PER

Modulation Period Adjustment for PLL1 Set and reset by software to adjust the modulation period of the clock spreading generator.
TPDFN_DIS1

Dithering TPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function.

0 (B_0x0): Dithering noise injection enabled (default after reset)

1 (B_0x1): Dithering noise injection disabled
RPDFN_DIS1

Dithering RPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function.

0 (B_0x0): Dithering noise injection enabled (default after reset)

1 (B_0x1): Dithering noise injection disabled
DWNSPREAD1

Spread spectrum clock generator mode for PLL1 Set and reset by software to select the clock spreading mode.

0 (B_0x0): Center-spread modulation selected (default after reset)

1 (B_0x1): Down-spread modulation selected
INC_STEP

Modulation Depth Adjustment for PLL1 Set and reset by software to adjust the modulation depth of the clock spreading generator.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32