DIVQ=B_0x0, DIVP=B_0x0, DIVR2=B_0x0
RCC PLL2 dividers configuration register 1
| DIVN2 | multiplication factor for PLL2 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL2ON = PLL2RDY = 0). …: not used … … Others: wrong configurations The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544 MHz if PLL2VCOSEL = 0 150 to 420 MHz if PLL2VCOSEL = 1 VCO output frequency = Fref2_ck x DIVN2, when fractional value 0 has been loaded into FRACN, with DIVN2 between 8 and 420 The input frequency Fref2_ck must be between 1 and 16MHz. 6 (B_0x006): wrong configuration 7 (B_0x007): DIVN2 = 8 128 (B_0x080): DIVN2 = 129 (default after reset) 419 (B_0x1A3): DIVN2 = 420 |
| DIVP | PLL2 DIVP division factor Set and reset by software to control the frequency of the pll2_p_ck clock. These bits can be written only when the PLL2DIVPEN = 0. … 0 (B_0x0): pll2_p_ck = vco2_ck 1 (B_0x1): pll2_p_ck = vco2_ck / 2 (default after reset) 2 (B_0x2): pll2_p_ck = vco2_ck / 3 3 (B_0x3): pll2_p_ck = vco2_ck / 4 127 (B_0x7F): pll2_p_ck = vco2_ck / 128 |
| DIVQ | PLL2 DIVQ division factor Set and reset by software to control the frequency of the pll2_q_ck clock. These bits can be written only when the PLL2DIVQEN = 0. … 0 (B_0x0): pll2_q_ck = vco2_ck 1 (B_0x1): pll2_q_ck = vco2_ck / 2 (default after reset) 2 (B_0x2): pll2_q_ck = vco2_ck / 3 3 (B_0x3): pll2_q_ck = vco2_ck / 4 127 (B_0x7F): pll2_q_ck = vco2_ck / 128 |
| DIVR2 | PLL2 DIVR division factor Set and reset by software to control the frequency of the pll2_r_ck clock. These bits can be written only when the PLL2DIVREN = 0. … 0 (B_0x0): pll2_r_ck = vco2_ck 1 (B_0x1): pll2_r_ck = vco2_ck / 2 (default after reset) 2 (B_0x2): pll2_r_ck = vco2_ck / 3 3 (B_0x3): pll2_r_ck = vco2_ck / 4 127 (B_0x7F): pll2_r_ck = vco2_ck / 128 |