DIVR3=B_0x0, DIVP=B_0x0, DIVQ=B_0x0
RCC PLL3 dividers configuration register 1
| DIVN3 | Multiplication factor for PLL3 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL3ON = PLL3RDY = 0). …: not used … … Others: wrong configurations The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544 MHz if PLL3VCOSEL = 0 150 to 420 MHz if PLL3VCOSEL = 1 VCO output frequency = Fref3_ck x DIVN3, when fractional value 0 has been loaded into FRACN, with: DIVN3 between 8 and 420 The input frequency Fref3_ck must be between 1 and 16MHz 6 (B_0x006): wrong configuration 7 (B_0x007): DIVN3 = 8 128 (B_0x080): DIVN3 = 129 (default after reset) 419 (B_0x1A3): DIVN3 = 420 |
| DIVP | PLL3 DIVP division factor Set and reset by software to control the frequency of the pll3_p_ck clock. These bits can be written only when the PLL3DIVPEN = 0. … 0 (B_0x0): pll3_p_ck = vco3_ck 1 (B_0x1): pll3_p_ck = vco3_ck / 2 (default after reset) 2 (B_0x2): pll3_p_ck = vco3_ck / 3 3 (B_0x3): pll3_p_ck = vco3_ck / 4 127 (B_0x7F): pll3_p_ck = vco3_ck / 128 |
| DIVQ | PLL3 DIVQ division factor Set and reset by software to control the frequency of the pll3_q_ck clock. These bits can be written only when the PLL3DIVQEN = 0. … 0 (B_0x0): pll3_q_ck = vco3_ck 1 (B_0x1): pll3_q_ck = vco3_ck / 2 (default after reset) 2 (B_0x2): pll3_q_ck = vco3_ck / 3 3 (B_0x3): pll3_q_ck = vco3_ck / 4 127 (B_0x7F): pll3_q_ck = vco3_ck / 128 |
| DIVR3 | PLL3 DIVR division factor Set and reset by software to control the frequency of the pll3_r_ck clock. These bits can be written only when the PLL3DIVREN = 0. … 0 (B_0x0): pll3_r_ck = vco3_ck 1 (B_0x1): pll3_r_ck = vco3_ck / 2 (default after reset) 2 (B_0x2): pll3_r_ck = vco3_ck / 3 3 (B_0x3): pll3_r_ck = vco3_ck / 4 127 (B_0x7F): pll3_r_ck = vco3_ck / 128 |