stm32 /stm32h7rs /STM32H7S /SAI1 /SAI_ASR

Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register.

0 (B_0x0): No overrun/underrun error.

1 (B_0x1): Overrun/underrun error detection.

Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register.

0 (B_0x0): No MUTE detection on the SD input line

1 (B_0x1): MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register.

0 (B_0x0): Clock configuration is correct

1 (B_0x1): Clock configuration does not respect the rule concerning the frame length specification defined in Section 55.4.6: Frame synchronization (configuration of FRL[7:0] bit in the SAI_xFRCR register)

FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register.

0 (B_0x0): No FIFO request.

1 (B_0x1): FIFO request to read or to write the SAI_xDR.

Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register.

0 (B_0x0): External AC97 Codec is ready

1 (B_0x1): External AC97 Codec is not ready

Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register.

0 (B_0x0): No error.

1 (B_0x1): Frame synchronization signal is detected earlier than expected.

Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register

0 (B_0x0): No error.

1 (B_0x1): Frame synchronization signal is not present at the right time.

FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). Others: Reserved

0 (B_0x0): FIFO empty (transmitter and receiver modes)

1 (B_0x1): FIFO UNDER OR EQUAL 1/4 but not empty (transmitter mode), FIFO < 1/4 but not empty (receiver mode)

2 (B_0x2): 1/4 < FIFO UNDER OR EQUAL 1/2 (transmitter mode), 1/4 UNDER OR EQUAL FIFO < 1/2 (receiver mode)

3 (B_0x3): 1/2 < FIFO UNDER OR EQUAL 3/4 (transmitter mode), 1/2 UNDER OR EQUAL FIFO < 3/4 (receiver mode)

4 (B_0x4): 3/4 < FIFO but not full (transmitter mode), 3/4 UNDER OR EQUAL FIFO but not full (receiver mode)

5 (B_0x5): FIFO full (transmitter and receiver modes)