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stm32 /stm32h7rs /STM32H7S /SAI1 /SAI_GCR

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Interpret as SAI_GCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SYNCIN 0 (B_0x0)SYNCOUT

SYNCOUT=B_0x0

Description

SAI global configuration register

Fields

SYNCIN

Synchronization inputs These bits are set and cleared by software. Refer to Table 418: External synchronization selection (TinyShark, Beluga and STM32U5_Cobra2M and 4M, Viper, Mustang, Python) for information on how to program this field. These bits must be set when both audio blocks (A and B) are disabled. They are meaningful if one of the two audio blocks is defined to operate in synchronous mode with an external SAI (SYNCEN[1:0] = 10 in SAI_ACR1 or in SAI_BCR1 registers).
SYNCOUT

Synchronization outputs These bits are set and cleared by software.

0 (B_0x0): No synchronization output signals. SYNCOUT[1:0] should be configured as No synchronization output signals when audio block is configured as SPDIF

1 (B_0x1): Block A used for further synchronization for others SAI

2 (B_0x2): Block B used for further synchronization for others SAI

3 (B_0x3): Reserved. These bits must be set when both audio block (A and B) are disabled.

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32