PWRSAV=B_0x0, CLKDIV=B_0x000, WIDBUS=B_0x0, BUSSPEED=B_0x0, HWFC_EN=B_0x0, NEGEDGE=B_0x0, DDR=B_0x0, SELCLKRX=B_0x0
SDMMC clock control register
| CLKDIV | Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (sdmmc_ker_ck) and the output clock (SDMMC_CK): SDMMC_CK frequency = sdmmc_ker_ck / [2 * CLKDIV]. 0x0XX: etc… 0xXXX: etc… 0 (B_0x000): SDMMC_CK frequency = sdmmc_ker_ck / 1 (Does not support DDR) 1 (B_0x001): SDMMC_CK frequency = sdmmc_ker_ck / 2 2 (B_0x002): SDMMC_CK frequency = sdmmc_ker_ck / 4 128 (B_0x080): SDMMC_CK frequency = sdmmc_ker_ck / 256 1023 (B_0x3FF): SDMMC_CK frequency = sdmmc_ker_ck / 2046 |
| PWRSAV | Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV: 0 (B_0x0): SDMMC_CK clock is always enabled 1 (B_0x1): SDMMC_CK is only enabled when the bus is active |
| WIDBUS | Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 0 (B_0x0): Default 1-bit wide bus mode: SDMMC_D0 used (Does not support DDR) 1 (B_0x1): 4-bit wide bus mode: SDMMC_D[3:0] used 2 (B_0x2): 8-bit wide bus mode: SDMMC_D[7:0] used |
| NEGEDGE | SDMMC_CK dephasing selection bit for data and command This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. Command and data changed on the sdmmc_ker_ck falling edge succeeding the rising edge of SDMMC_CK. SDMMC_CK edge occurs on sdmmc_ker_ck rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: Command changed on the sdmmc_ker_ck falling edge succeeding the rising edge of SDMMC_CK. Data changed on the sdmmc_ker_ck falling edge succeeding a SDMMC_CK edge. SDMMC_CK edge occurs on sdmmc_ker_ck rising edge. Command and data changed on the same sdmmc_ker_ck rising edge generating the SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 1: Command changed on the same sdmmc_ker_ck rising edge generating the SDMMC_CK falling edge. Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. SDMMC_CK edge occurs on sdmmc_ker_ck rising edge. 0 (B_0x0): When clock division >1 (CLKDIV > 0) & DDR = 0: 1 (B_0x1): When clock division >1 (CLKDIV > 0) & DDR = 0: |
| HWFC_EN | Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, see SDMMC status register definition in Section 58.10.11. 0 (B_0x0): Hardware flow control is disabled 1 (B_0x1): Hardware flow control is enabled |
| DDR | Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate must only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate must only be selected with clock division >1. (CLKDIV > 0) 0 (B_0x0): SDR Single data rate signaling 1 (B_0x1): DDR double data rate signaling |
| BUSSPEED | Bus speed for selection of SDMMC operating modes This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 0 (B_0x0): DS, HS, SDR12, SDR25, Legacy compatible, High speed SDR, High speed DDR bus speed mode selected 1 (B_0x1): SDR50, DDR50, SDR104, HS200 bus speed mode selected. |
| SELCLKRX | Receive clock selection These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) 0 (B_0x0): sdmmc_io_in_ck selected as receive clock 1 (B_0x1): SDMMC_CKIN feedback clock selected as receive clock 2 (B_0x2): sdmmc_fb_ck tuned feedback clock selected as receive clock. 3 (B_0x3): Reserved (select sdmmc_io_in_ck) |