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stm32 /stm32h7rs /STM32H7S /SDMMC1 /SDMMC_IDMABASER

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Interpret as SDMMC_IDMABASER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0IDMABASE

Description

SDMMC IDMA buffer base address register

Fields

IDMABASE

Buffer memory base address bits [31:2], must be word aligned (bit [1:0] are always 0 and read only) This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1).

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32