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stm32 /stm32h7rs /STM32H7S /SPDIFRX /SPDIFRX_FMT0_DR_alternate2

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Interpret as SPDIFRX_FMT0_DR_alternate2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DRNL10DRNL2

Description

SPDIFRX data input register

Fields

DRNL1

data value This field contains the channel B
DRNL2

data value This field contains the channel A

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32