Regviz

stm32 /stm32h7rs /STM32H7S /TIM3 /TIM3_ARR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TIM3_ARR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32h7rs/STM32H7R/TIM3/TIM3_ARR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ARR

Description

TIM3 auto-reload register

Fields

ARR

Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 65.4.3: Time-base unit on page 3820 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. Non-dithering mode (DITHEN = 0) The register holds the auto-reload value. Dithering mode (DITHEN = 1) The register holds the integer part in ARR[31:4]. The ARR[3:0] bitfield contains the dithered part.

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32