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stm32 /stm32h7rs /STM32H7S /TIM3 /TIM3_CNT

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Interpret as TIM3_CNT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CNT0 (UIFCPY_CNT)UIFCPY_CNT

Description

TIM3 counter

Fields

CNT

Least significant part of counter value Non-dithering mode (DITHEN = 0) The register holds the counter value. Dithering mode (DITHEN = 1) The register holds the non-dithered part in CNT[30:0]. The fractional part is not available.
UIFCPY_CNT

Value depends on IUFREMAP in TIMx_CR1. If UIFREMAP = 0 CNT[31]: Most significant bit of counter value If UIFREMAP = 1 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32