SMIE=B_0x0, FTIE=B_0x0, DMAEN=B_0x0, FTHRES=B_0x0, EN=B_0x0, TOIE=B_0x0, ABORT=B_0x0, APMS=B_0x0, TEIE=B_0x0, DMM=B_0x0, CSSEL=B_0x0, TCEN=B_0x0, PMM=B_0x0, TCIE=B_0x0, MSEL=B_0x0, FMODE=B_0x0
XSPI control register
| EN | Enable This bit enables the XSPI. The DMA request can be aborted without having received the ACK in case this EN bit is cleared during the operation. Note: In case this bit is set to 0 during a DMA transfer, the REQ signal to DMA returns to inactive state without waiting for the ACK signal from DMA to be active. 0 (B_0x0): XSPI disabled 1 (B_0x1): XSPI enabled |
| ABORT | Abort request This bit aborts the on-going command sequence. It is automatically reset once the abort is completed. This bit stops the current transfer. Note: This bit is always read as 0. 0 (B_0x0): no abort requested 1 (B_0x1): abort requested |
| DMAEN | DMA enable In indirect mode, the DMA can be used to input or output data via XSPI_DR. DMA transfers are initiated when FTF is set. Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with the DMA. Do not write this bit during DMA operation. 0 (B_0x0): DMA disabled for indirect mode 1 (B_0x1): DMA enabled for indirect mode |
| TCEN | Timeout counter enable This bit is valid only when the memory-mapped mode (FMODE[1:0] = 11) is selected. This bit enables the timeout counter. Note: This bit can be modified only when BUSY = 0. 0 (B_0x0): timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely after an access in memory-mapped mode. 1 (B_0x1): timeout counter is enabled, and thus the chip-select is released in the memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity. |
| DMM | Dual-memory configuration This bit activates the dual-memory configuration, where two external devices are used simultaneously to double the throughput and the capacity Note: This bit can be modified only when BUSY = 0. 0 (B_0x0): dual-memory configuration disabled 1 (B_0x1): dual-memory configuration enabled |
| FTHRES | FIFO threshold level This field defines, in indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in XSPI_SR, to be set. … Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES[5:0] value. 0 (B_0x0): FTF is set if there are one or more free bytes available to be written to in the FIFO 1 (B_0x1): FTF is set if there are two or more free bytes available to be written to in the FIFO 63 (B_0x3F): FTF is set if there are 64 free bytes available to be written to in the FIFO |
| TEIE | Transfer error interrupt enable This bit enables the transfer error interrupt. 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled |
| TCIE | Transfer complete interrupt enable This bit enables the transfer complete interrupt. 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled |
| FTIE | FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt. 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled |
| SMIE | Status match interrupt enable This bit enables the status match interrupt. 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled |
| TOIE | Timeout interrupt enable This bit enables the timeout interrupt. 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled |
| APMS | Automatic status-polling mode stop This bit determines if the automatic status-polling is stopped after a match. Note: This bit can be modified only when BUSY = 0. 0 (B_0x0): Automatic status-polling mode is stopped only by abort or by disabling the XSPI. 1 (B_0x1): Automatic status-polling mode stops as soon as there is a match. |
| PMM | Polling match mode This bit indicates which method must be used to determine a match during the automatic status-polling mode. Note: This bit can be modified only when BUSY = 0. 0 (B_0x0): AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register. 1 (B_0x1): OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register. |
| CSSEL | chip select selection This bit indicates if the XSPI must activate NCS1 or NCS2. Note: This bit can be modified only when BUSY = 0. 0 (B_0x0): NCS1 active 1 (B_0x1): NCS2 active |
| FMODE | Functional mode This field defines the XSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE[1:0] value. If FMODE[1:0] and FTHRES[4:0] are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state. Note: This bitfield can be modified only when BUSY = 0. 0 (B_0x0): indirect-write mode 1 (B_0x1): indirect-read mode 2 (B_0x2): automatic status-polling mode 3 (B_0x3): memory-mapped mode |
| MSEL | Flash select 0 (B_0x0): data exchanged over IO[3:0] 1 (B_0x1): data exchanged over IO[7:4] 2 (B_0x2): data exchanged over IO[11:8] 3 (B_0x3): data exchanged over IO[15:12] |