MTYP=B_0x0, FRCK=B_0x0, CKMODE=B_0x0, CSHT=B_0x0
XSPI device configuration register 1
| CKMODE | clock mode 0/mode 3 This bit indicates the level taken by the CLK between commands (when NCS = 1). 0 (B_0x0): CLK must stay low while NCS is high (chip-select released), referred to as clock mode 0. 1 (B_0x1): CLK must stay high while NCS is high (chip-select released), referred to as clock mode 3. |
| FRCK | Free running clock This bit configures the free running clock. 0 (B_0x0): CLK is not free running. 1 (B_0x1): CLK is free running (always provided). |
| CSHT | Chip-select high time CSHT + 1 defines the minimum number of CLK cycles where the chip-select (NCS) must remain high between commands issued to the external device. … 0 (B_0x0): NCS stays high for at least 1 cycle between external device commands. 1 (B_0x1): NCS stays high for at least 2 cycles between external device commands. 63 (B_0x3F): NCS stays high for at least 64 cycles between external device commands. |
| DEVSIZE | Device size This field defines the size of the external device using the following formula: Number of bytes in device = 2[DEVSIZE+1]. DEVSIZE+1 is effectively the number of address bits required to address the external device. The device capacity can be up to 4 Gbytes (addressed using 32-bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256 Mbytes. In regular-command protocol, if DMM = 1, DEVSIZE[4:0] indicates the total capacity of the two devices together. |
| MTYP | Memory type This bit indicates the type of memory to be supported. Note: In this mode, DQS signal polarity is inverted with respect to the memory clock signal. This is the default value and care must be taken to change MTYP[2:0] for memories different from Micron. Others: Reserved 0 (B_0x0): Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes. 1 (B_0x1): Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes. 2 (B_0x2): Standard mode 3 (B_0x3): Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes with dedicated address mapping. 4 (B_0x4): HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit DTR mode must be selected. 5 (B_0x5): HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be non-cacheable, or indirect read/write modes must be used. |