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stm32 /stm32h7rs /STM32H7S /XSPI1 /XSPI_DCR4

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Interpret as XSPI_DCR4

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)REFRESH

REFRESH=B_0x0

Description

XSPI device configuration register 4

Fields

REFRESH

Refresh rate This field enables the refresh rate feature. The NCS is released every REFRESH + 1 clock cycles for writes, and REFRESH + 4 clock cycles for reads. Note: These two values can be extended with few clock cycles when refresh occurs during a byte transmission in single-, dual- or quad-SPI mode, because the byte transmission must be completed. Others: maximum communication length is set to REFRESH + 1 clock cycles.

0 (B_0x0): refresh disabled

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32