Regviz

stm32 /stm32l0 /STM32L053 /TIM21 /OR

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Interpret as OR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ETR_RMP 0TI1_RMP 0 (TI2_RMP)TI2_RMP

Description

TIM21 option register

Fields

ETR_RMP

Timer21 ETR remap
TI1_RMP

Timer21 TI1
TI2_RMP

Timer21 TI2

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32