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stm32 /stm32l0 /STM32L062 /ADC /CFGR2

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Interpret as CFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OVSE)OVSE 0OVSR0OVSS0 (TOVS)TOVS 0CKMODE

Description

configuration register 2

Fields

OVSE

Oversampler Enable
OVSR

Oversampling ratio
OVSS

Oversampling shift
TOVS

Triggered Oversampling
CKMODE

ADC clock mode

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32