Regviz

stm32 /stm32l0 /STM32L063 /LCD /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LCDEN)LCDEN 0 (VSEL)VSEL 0DUTY0BIAS 0 (MUX_SEG)MUX_SEG

Description

control register

Fields

LCDEN

LCD controller enable
VSEL

Voltage source selection
DUTY

Duty selection
BIAS

Bias selector
MUX_SEG

Mux segment enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32