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stm32 /stm32l0 /STM32L0x1 /Flash /ACR

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Interpret as ACR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LATENCY)LATENCY 0 (PRFTEN)PRFTEN 0 (SLEEP_PD)SLEEP_PD 0 (RUN_PD)RUN_PD 0 (DISAB_BUF)DISAB_BUF 0 (PRE_READ)PRE_READ

Description

Access control register

Fields

LATENCY

Latency
PRFTEN

Prefetch enable
SLEEP_PD

Flash mode during Sleep
RUN_PD

Flash mode during Run
DISAB_BUF

Disable Buffer
PRE_READ

Pre-read data address

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32