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stm32 /stm32l0 /STM32L0x1 /LPUART1 /CR2

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Interpret as CR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ADDM7)ADDM7 0 (CLKEN)CLKEN 0STOP 0 (SWAP)SWAP 0 (RXINV)RXINV 0 (TXINV)TXINV 0 (TAINV)TAINV 0 (MSBFIRST)MSBFIRST 0ADD0_30ADD4_7

Description

Control register 2

Fields

ADDM7

7-bit Address Detection/4-bit Address Detection
CLKEN

Clock enable
STOP

STOP bits
SWAP

Swap TX/RX pins
RXINV

RX pin active level inversion
TXINV

TX pin active level inversion
TAINV

Binary data inversion
MSBFIRST

Most significant bit first
ADD0_3

Address of the USART node
ADD4_7

Address of the USART node

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32