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stm32 /stm32l0 /STM32L0x1 /LPUART1 /CR3

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Interpret as CR3

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EIE)EIE 0 (HDSEL)HDSEL 0 (DMAR)DMAR 0 (DMAT)DMAT 0 (RTSE)RTSE 0 (CTSE)CTSE 0 (CTSIE)CTSIE 0 (OVRDIS)OVRDIS 0 (DDRE)DDRE 0 (DEM)DEM 0 (DEP)DEP 0WUS0 (WUFIE)WUFIE

Description

Control register 3

Fields

EIE

Error interrupt enable
HDSEL

Half-duplex selection
DMAR

DMA enable receiver
DMAT

DMA enable transmitter
RTSE

RTS enable
CTSE

CTS enable
CTSIE

CTS interrupt enable
OVRDIS

Overrun Disable
DDRE

DMA Disable on Reception Error
DEM

Driver enable mode
DEP

Driver enable polarity selection
WUS

Wakeup from Stop mode interrupt flag selection
WUFIE

Wakeup from Stop mode interrupt enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32