Regviz

stm32 /stm32l0 /STM32L0x1 /TIM2 /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (UIF)UIF 0 (CC1IF)CC1IF 0 (CC2IF)CC2IF 0 (CC3IF)CC3IF 0 (CC4IF)CC4IF 0 (TIF)TIF 0 (CC1OF)CC1OF 0 (CC2OF)CC2OF 0 (CC3OF)CC3OF 0 (CC4OF)CC4OF

Description

status register

Fields

UIF

Update interrupt flag
CC1IF

Capture/compare 1 interrupt flag
CC2IF

Capture/Compare 2 interrupt flag
CC3IF

Capture/Compare 3 interrupt flag
CC4IF

Capture/Compare 4 interrupt flag
TIF

Trigger interrupt flag
CC1OF

Capture/Compare 1 overcapture flag
CC2OF

Capture/compare 2 overcapture flag
CC3OF

Capture/Compare 3 overcapture flag
CC4OF

Capture/Compare 4 overcapture flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32