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stm32 /stm32l0 /STM32L0x2 /CRS /CFGR

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Interpret as CFGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RELOAD0FELIM0SYNCDIV 0SYNCSRC 0 (SYNCPOL)SYNCPOL

Description

configuration register

Fields

RELOAD

Counter reload value
FELIM

Frequency error limit
SYNCDIV

SYNC divider
SYNCSRC

SYNC signal source selection
SYNCPOL

SYNC polarity selection

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32