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stm32 /stm32l0 /STM32L0x2 /MPU /MPU_CTRL

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Interpret as MPU_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENABLE)ENABLE 0 (HFNMIENA)HFNMIENA 0 (PRIVDEFENA)PRIVDEFENA

Description

MPU control register

Fields

ENABLE

Enables the MPU
HFNMIENA

Enables the operation of MPU during hard fault
PRIVDEFENA

Enable priviliged software access to default memory map

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32