Regviz

stm32 /stm32l1 /STM32L100 /TIM6 /SR

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Interpret as SR

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https://regviz.com/r/stm32/stm32l1/STM32L151/TIM6/SR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (UIF)UIF

Description

TIM6 status register

Fields

UIF

Update interrupt flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32