Regviz

stm32 /stm32l1 /STM32L162 /LCD /CLR

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Interpret as CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SOFC)SOFC 0 (UDDC)UDDC

Description

clear register

Fields

SOFC

Start of frame flag clear
UDDC

Update display done clear

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32