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stm32 /stm32l4+ /STM32L4Q5 /LTCD /CDSR

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Interpret as CDSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (VDES)VDES 0 (HDES)HDES 0 (VSYNCS)VSYNCS 0 (HSYNCS)HSYNCS

Description

LTDC Current Display Status Register

Fields

VDES

Vertical Data Enable display Status
HDES

Horizontal Data Enable display Status
VSYNCS

Vertical Synchronization display Status
HSYNCS

Horizontal Synchronization display Status

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32