Regviz

stm32 /stm32l4+ /STM32L4Q5 /RTC /ALRBBINR

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Interpret as ALRBBINR

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https://regviz.com/r/stm32/stm32l4+/STM32L4P5/RTC/ALRBBINR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SS

Description

alarm B binary mode register

Fields

SS

Synchronous counter alarm value in Binary mode

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32