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stm32 /stm32l4+ /STM32L4Q5 /RTC /ALRMASSR

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Interpret as ALRMASSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SS0MASKSS0 (SSCLR)SSCLR

Description

alarm A sub second register

Fields

SS

Sub seconds value
MASKSS

Mask the most-significant bits starting at this bit
SSCLR

Clear synchronous counter on alarm

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32