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stm32 /stm32l4+ /STM32L4Q5 /SDMMC1 /IDMABASE0R

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Interpret as IDMABASE0R

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0IDMABASE0

Description

IDMA buffer 0 base address register

Fields

IDMABASE0

Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only)

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32