stm32 /stm32l4+ /STM32L4Q5 /TIM2 /TIM2_TISEL

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Interpret as TIM2_TISEL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TI1SEL0 (B_0x0)TI2SEL0 (B_0x0)TI3SEL0 (B_0x0)TI4SEL

TI4SEL=B_0x0, TI1SEL=B_0x0, TI3SEL=B_0x0, TI2SEL=B_0x0

Description

TIM2 timer input selection register

Fields

TI1SEL

TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved

0 (B_0x0): TIM2_CH1 input

TI2SEL

TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved

0 (B_0x0): TIM2_CH2 input

TI3SEL

TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. Others: Reserved

0 (B_0x0): TIM2_CH3 input

TI4SEL

TI4[0] to TI4[15] input selection These bits select the TI4[0] to TI4[15] input source. Others: Reserved

0 (B_0x0): TIM2_CH4 input

1 (B_0x1): COMP1 output

2 (B_0x2): COMP2 output

3 (B_0x3): COMP1 output OR COMP2 output

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