Regviz

stm32 /stm32l4+ /STM32L4R5 /ADC /JSQR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as JSQR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32f3/STM32F302/ADC1/JSQR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0JL0JEXTSEL0JEXTEN 0JSQ10JSQ20JSQ30JSQ4

Description

injected sequence register

Fields

JL

JL
JEXTSEL

JEXTSEL
JEXTEN

JEXTEN
JSQ1

JSQ1
JSQ2

JSQ2
JSQ3

JSQ3
JSQ4

JSQ4

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32