Regviz

stm32 /stm32l4+ /STM32L4R5 /AES /SR

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Interpret as SR

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https://regviz.com/r/stm32/stm32f4/STM32F413/AES/SR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CCF)CCF 0 (RDERR)RDERR 0 (WRERR)WRERR

Description

status register

Fields

CCF

Computation complete flag
RDERR

Read error flag
WRERR

Write error flag

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32