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stm32 /stm32l4+ /STM32L4R5 /DAC /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMAUDR1)DMAUDR1 0 (CAL_FLAG1)CAL_FLAG1 0 (BWST1)BWST1 0 (DMAUDR2)DMAUDR2 0 (CAL_FLAG2)CAL_FLAG2 0 (BWST2)BWST2

Description

status register

Fields

DMAUDR1

DAC channel1 DMA underrun flag
CAL_FLAG1

DAC Channel 1 calibration offset status
BWST1

DAC Channel 1 busy writing sample time flag
DMAUDR2

DAC channel2 DMA underrun flag
CAL_FLAG2

DAC Channel 2 calibration offset status
BWST2

DAC Channel 2 busy writing sample time flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32