Regviz

stm32 /stm32l4+ /STM32L4R5 /DMAMUX1 /CSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CSR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32l4+/STM32L4Q5/DMAMUX1/CSR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SOF0)SOF0 0 (SOF1)SOF1 0 (SOF2)SOF2 0 (SOF3)SOF3 0 (SOF4)SOF4 0 (SOF5)SOF5 0 (SOF6)SOF6 0 (SOF7)SOF7 0 (SOF8)SOF8 0 (SOF9)SOF9 0 (SOF10)SOF10 0 (SOF11)SOF11 0 (SOF12)SOF12 0 (SOF13)SOF13

Description

channel status register

Fields

SOF0

Synchronization overrun event flag
SOF1

Synchronization overrun event flag
SOF2

Synchronization overrun event flag
SOF3

Synchronization overrun event flag
SOF4

Synchronization overrun event flag
SOF5

Synchronization overrun event flag
SOF6

Synchronization overrun event flag
SOF7

Synchronization overrun event flag
SOF8

Synchronization overrun event flag
SOF9

Synchronization overrun event flag
SOF10

Synchronization overrun event flag
SOF11

Synchronization overrun event flag
SOF12

Synchronization overrun event flag
SOF13

Synchronization overrun event flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32