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stm32 /stm32l4+ /STM32L4R5 /OCTOSPI1 /DCR1

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Interpret as DCR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CKMODE)CKMODE 0 (FRCK)FRCK 0 (DLYBYP)DLYBYP 0CSHT0DEVSIZE0MTYP

Description

device configuration register

Fields

CKMODE

Mode 0 / mode 3
FRCK

Free running clock
DLYBYP

Delay block bypass
CSHT

Chip-select high time
DEVSIZE

Device size
MTYP

Memory type

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32