Regviz

stm32 /stm32l4+ /STM32L4R5 /OCTOSPI1 /DLR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DLR

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https://regviz.com/r/stm32/stm32f4/STM32F412/QUADSPI/DLR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DL

Description

data length register

Fields

DL

Data length

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32