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stm32 /stm32l4+ /STM32L4R5 /SCB /SCR

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Interpret as SCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SLEEPONEXIT)SLEEPONEXIT 0 (SLEEPDEEP)SLEEPDEEP 0 (SEVEONPEND)SEVEONPEND

Description

System control register

Fields

SLEEPONEXIT

SLEEPONEXIT
SLEEPDEEP

SLEEPDEEP
SEVEONPEND

Send Event on Pending bit

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32