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stm32 /stm32l4+ /STM32L4R5 /SYSCFG /CFGR2

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Interpret as CFGR2

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31282724232019161512118743000000000000000000000000000000000000000000 (CLL)CLL0 (SPL)SPL0 (PVDL)PVDL0 (ECCL)ECCL0 (SPF)SPF

Description

CFGR2

Fields

CLL

Cortex-M4 LOCKUP (Hardfault) output enable bit
SPL

SRAM2 parity lock bit
PVDL

PVD lock enable bit
ECCL

ECC Lock
SPF

SRAM2 parity error flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32