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stm32 /stm32l4+ /STM32L4R5 /TIM15 /TIM15_TISEL

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Interpret as TIM15_TISEL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TI1SEL0 (B_0x0)TI2SEL

TI1SEL=B_0x0, TI2SEL=B_0x0

Description

TIM15 input selection register

Fields

TI1SEL

selects TI1[0] to TI1[15] input Other: Reserved

0 (B_0x0): TIM15_CH1 input

1 (B_0x1): TIM2_CH1 input

2 (B_0x2): TIM3_CH1 input

3 (B_0x3): TIM4_CH1 input

4 (B_0x4): LSE

5 (B_0x5): CSI

6 (B_0x6): MCO2
TI2SEL

selects TI2[0] to TI2[15] input Others: Reserved

0 (B_0x0): TIM15_CH2 input

1 (B_0x1): TIM2_CH2 input

2 (B_0x2): TIM3_CH2 input

3 (B_0x3): TIM4_CH2 input

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32