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stm32 /stm32l4+ /STM32L4R5 /TIM17 /TIM17_TISEL

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Interpret as TIM17_TISEL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TI1SEL

TI1SEL=B_0x0

Description

TIM17 input selection register

Fields

TI1SEL

selects TI1[0] to TI1[15] input Others: Reserved

0 (B_0x0): TIM17_CH1 input

2 (B_0x2): HSE_1MHz

3 (B_0x3): MCO1

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32