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stm32 /stm32l4+ /STM32L4R7 /ADC_Common /CCR

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Interpret as CCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DUAL0DELAY0 (DMACFG)DMACFG 0MDMA 0CKMODE 0PRESC0 (VREFEN)VREFEN 0 (CH17SEL)CH17SEL 0 (CH18SEL)CH18SEL

Description

ADC common control register

Fields

DUAL

Dual ADC mode selection
DELAY

Delay between 2 sampling phases
DMACFG

DMA configuration (for multi-ADC mode)
MDMA

Direct memory access mode for multi ADC mode
CKMODE

ADC clock mode
PRESC

ADC prescaler
VREFEN

VREFINT enable
CH17SEL

CH17 selection
CH18SEL

CH18 selection

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32