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stm32 /stm32l4+ /STM32L4R7 /SCB /HFSR

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Interpret as HFSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (VECTTBL)VECTTBL 0 (FORCED)FORCED 0 (DEBUG_VT)DEBUG_VT

Description

Hard fault status register

Fields

VECTTBL

Vector table hard fault
FORCED

Forced hard fault
DEBUG_VT

Reserved for Debug use

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32