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stm32 /stm32l4+ /STM32L4R9 /DMAMUX1 /C5CR

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Interpret as C5CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DMAREQ_ID0 (SOIE)SOIE 0 (EGE)EGE 0 (SE)SE 0SPOL 0NBREQ0SYNC_ID

Description

channel 5 configuration register

Fields

DMAREQ_ID

DMA request identification
SOIE

Synchronization overrun interrupt enable
EGE

Event generation enable
SE

Synchronization enable
SPOL

Synchronization polarity
NBREQ

Number of DMA requests minus 1 to forward
SYNC_ID

Synchronization identification

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32