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stm32 /stm32l4+ /STM32L4R9 /DSI /DSI_TCCR0

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Interpret as DSI_TCCR0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LPRX_TOCNT0HSTX_TOCNT

Description

DSI Host Timeout Counter Configuration Register 0

Fields

LPRX_TOCNT

Low-power Reception Timeout Counter
HSTX_TOCNT

High-Speed Transmission Timeout Counter

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32