Regviz

stm32 /stm32l4+ /STM32L4R9 /SCB /CCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32f1/STM32F101/SCB/CCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NONBASETHRDENA)NONBASETHRDENA 0 (USERSETMPEND)USERSETMPEND 0 (UNALIGN__TRP)UNALIGN__TRP 0 (DIV_0_TRP)DIV_0_TRP 0 (BFHFNMIGN)BFHFNMIGN 0 (STKALIGN)STKALIGN

Description

Configuration and control register

Fields

NONBASETHRDENA

Configures how the processor enters Thread mode
USERSETMPEND

USERSETMPEND
UNALIGN__TRP

UNALIGN_ TRP
DIV_0_TRP

DIV_0_TRP
BFHFNMIGN

BFHFNMIGN
STKALIGN

STKALIGN

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32