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stm32 /stm32l4+ /STM32L4S5 /ADC /CFGR2

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Interpret as CFGR2

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31282724232019161512118743000000000000000000000000000000000000000000 (ROVSE)ROVSE0 (JOVSE)JOVSE0OVSR0OVSS0 (TROVS)TROVS0 (ROVSM)ROVSM

Description

configuration register

Fields

ROVSE

DMAEN
JOVSE

DMACFG
OVSR

RES
OVSS

ALIGN
TROVS

Triggered Regular Oversampling
ROVSM

EXTEN

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32