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stm32 /stm32l4+ /STM32L4S5 /DMAMUX1 /RG1CR

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Interpret as RG1CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SIG_ID0 (OIE)OIE 0 (GE)GE 0GPOL 0GNBREQ

Description

request generator channel 1 configuration register

Fields

SIG_ID

Signal identification
OIE

Trigger overrun interrupt enable
GE

DMA request generator channel 1 enable
GPOL

DMA request generator trigger polarity
GNBREQ

Number of DMA requests to be generated minus 1

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32