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stm32 /stm32l4+ /STM32L4S5 /OCTOSPIM /P1CR

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Interpret as P1CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLKEN)CLKEN 0 (CLKSRC)CLKSRC 0 (DQSEN)DQSEN 0 (DQSSRC)DQSSRC 0 (NCSEN)NCSEN 0 (NCSSRC)NCSSRC 0 (IOLEN)IOLEN 0IOLSRC 0 (IOHEN)IOHEN 0IOHSRC

Description

OctoSPI IO Manager Port 1 Configuration Register

Fields

CLKEN

CLK/CLK Enable for Port
CLKSRC

CLK/CLK Source for Port
DQSEN

DQS Enable for Port
DQSSRC

DQS Source for Port
NCSEN

CS Enable for Port
NCSSRC

CS Source for Port
IOLEN

Enable for Port
IOLSRC

Source for Port
IOHEN

Enable for Port n
IOHSRC

Source for Port

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32