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stm32 /stm32l4+ /STM32L4S7 /DMA2D /BGPFCCR

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Interpret as BGPFCCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CM0 (CCM)CCM 0 (START)START 0CS0AM0 (AI)AI 0 (RBS)RBS 0ALPHA

Description

background PFC control register

Fields

CM

Color mode
CCM

CLUT Color mode
START

Start
CS

CLUT size
AM

Alpha mode
AI

Alpha Inverted
RBS

Red Blue Swap
ALPHA

Alpha value

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32