stm32 /stm32l4+ /STM32L4S7 /HASH /SR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SR

31282724232019161512118743000000000000000000000000000000000000000000 (DINIS)DINIS0 (DCIS)DCIS0 (DMAS)DMAS0 (BUSY)BUSY

Description

status register

Fields

DINIS

Data input interrupt status

DCIS

Digest calculation completion interrupt status

DMAS

DMA Status

BUSY

Busy bit

Links

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